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document number: mc33813 rev. 1.0, 8/2012 freescale semiconductor ? product preview ? freescale semiconductor, in c., 2012. all rights reserved. *this document contains certain information on a new product. ? specifications and information herei n are subject to change without notice. one cylinder small engine control ic the 33813 is an engine control analog power ic intended for one cylinder motorcycle and other small engine cont rol applications. the ic consists of five integrated low side drivers, tw o pre-drivers, a variable reluctance sensor (vrs) input circuit, a voltage pre-regulator using an external pass transistor, and two 5.0 volt internal regulators, one for the microcontroller unit (mcu) v cc supply and the other for use as a protected sensor supply. also included is an mcu reset control circuit with watchdog, an iso 9141 k-line interface for diagnostic communication and a serial peripheral interface (spi). the five low side drivers are intended for driving a fuel injector, a lamp, two relays or other loads, and a tachometer. the pre- driver is intended to drive igbt or mosfet transistors to control ignition coils, and/or a hego heater. the device is packaged in a 48 pin lqfp- ep with an exposed pad. features : ? operates over a supply voltage range of 4.5 v ? v pwr ? 36 v ? logic stability guaranteed down to 2.5 v ? one fuel injector driver - typical of 1.3 a ? one ignition igbt or general purpose gate pre-driver ? one o2 sensor (hego) heater general purpose gate pre-driver ? relay 1 driver, typically 2.0 a, can be used for fuel pump control ? relay 2 driver, typically 1.0 a, can be used as power relay control ? lamp driver, typically 1.0 a can also be used to drive an led ?v prot protected sensor supply tracks v cc +5.0 v regulator ? mcu reset generator -system integrity monitor (watchdog) ?v pp pre-regulator provides power for v cc and v prot regulators ? independent fault protection with all faults reported via the spi ? iso 9141 k-line interface for communicating diagnostic messages ? start-up / shut-down control and power sequence logic ? interfaces directly to mcu using a 5.0 v spi and logic i/o ? differential / single-ended vrs conditioning circuit with auto/manual selected thresholds and filter time s with digital and tachometer outputs figure 1. 33813 simplified application diagram 33813 98ASA00173D ae suffix (pb-free) 48-pin lqfp - ep applications small engine control for: ? lawn mowers ? motor scooters ? small motorcycles ? lawn trimmers ? snow blowers ? chain saws ? gasoline-driven electrical generators ? outboard motors one cylinder small engine control ic vpwr spi vrsout mrx mc33813 spi v bat o2hout lampout mcu resetb injout1 rout1 relay 1 mil o2 heater v bat v bat injector resetb crankshaft vrs vrsp vrsn v cc mtx injin1 o2hin gpio keysw rout2 vppsens gnd +5.0 v ignin1 ignout1 iso9141 iso9141 ignfb1 o2hfb vppref 4 v bat keyswitch relay 2 vprot 5.0 v sensor supply gpio gpio gpio gpio gpio v bat (power) (fuel pump) tachout tachometer vcc batsw ignsensp ignsensn o2hsensp o2hsensn gpio gpio rin1 rin2 gpio
analog integrated circuit device data ? freescale semiconductor 2 33813 1 orderable parts table 1. orderable part variations part number (1) notes temperature (t a ) package pc33813ae -40 to 125 c 48 lqfp-ep notes 1. to order parts in tape & reel, add the r2 suffix to the part number.
analog integrated circuit device data ? freescale semiconductor 3 33813 table of contents 1 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5 typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 general ic functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 mcu spi interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 functional device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.1 package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
analog integrated circuit device data ? freescale semiconductor 4 33813 2 internal block diagram figure 2. simplified internal block diagram oscillator injin1 v pp vpwr ignin1 so si sclk csb v cc logic control spi interface gate control current limit temperature limit short/open (1 of 6 shown) + r s llimit vclamp ? typical of all 6 driver outputs 75 a injout1 v ppref bandgap + ? parallel control under-voltage por, v10.0 analog v2.5 logic bias vrsn vppsens vrs circuit vrsout rout2 iso9141 controller mrx mtx lampout o2hout v cc resetb keysw start logic iso9141 v cc ignition 1 ignout1 pre-drivers ignfb1 o2hfb o2 heater gnd o2hin injgnd1 injgnd2 tachout to tachout driver v prot to rout2 watchdog (spi control) rout1 vcc pre- regulator over-voltage tracking +5.0 v regulator +5.0 v v pwr vanalog v logic batsw parallel control spi control driver + ? + ? llimit llimit o2hsensp ignsensp ignsensn o2hsensn to logic control to logic control rin1 rin2 note: all current sinks and sources ~ 50a except where indicated regulator & registers rgnd1 rgnd2 divide by ?n? n=1-32 divider (spi) v cc sleep/run vrsp
analog integrated circuit device data ? freescale semiconductor 5 33813 3 pin connections 3.1 pinout diagram figure 3. 33813 pin connections 3.2 pin definitions table 2. 33813 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 24 . pin pin name pin function formal name description 1 o2hfb input o2 sensor heater feedback input voltage feedback from drain of o2 sensor heater driver fet 2 o2hout output o2 sensor heater output pre-driver output for o2 sensor heater driven by spi input or o2hin pin 3 ignsensp input ignition current sense input positive positive input to the ignition cu rrent sense differential amplifier used to measure current in igbt emitter resistor for ignout1 and ignout2, if used. 4 ignsensn input ignition current sense input negative negative input to the ignition curr ent sense differential amplifier used to measure current in igbt emitter resistor for ignout1 and ignout2, if used. 5 o2hsensn input o2 heater current sense input negative negative input to the o2 heater current sense differential amplifier used to measure current in of o2 heater driver mosfet source resistor, if used. o2hfb o2hout ignsensp ignsensn oh2sensn vrsp vrsn csb vpwr sclk si vppref gnd so vcc vppsens resetb vprot lampout rgnd2 rout2 nc nc tachout mrx mtx batsw injin1 nc ignin1 o2hin rin2 rin1 keysw injgnd2 nc rgnd1 rout1 injgnd1 injout1 iso9141 ignfb1 ignout1 nc nc oh2sensp vrsout nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 transparent top view
analog integrated circuit device data ? freescale semiconductor 6 33813 6 o2hsensp input o2 heater current sense input positive positive input to the o2 heater current sense differential amplifier used to measure current in of o2 heater driver mosfet source resistor, if used. 7 vrsout output vrs conditioned output 5.0 v logic level output from conditioned vrs differential inputs vrsp, vrsn 8 vrsp input variable reluctance sensor positive input the vrsp and vrsn form a differential input for the variable reluctance sensor attached to the crankshaft toothed wheel. 9 vrsn input variable reluctance sensor negative input the vrsp and vrsn form a differential input for the variable reluctance sensor attached to the crankshaft toothed wheel. 10 csb input spi chip select the chip select input pin is an active low signal sent by the mcu to indicate that the device is being addressed. 11 vpwr supply input main voltage supply input vpwr is the main voltage supply input for the device. connected to a 12 volt battery (should have reverse battery protection and adequate transient protection.) 12 sclk input spi clock input the sclk input pin is used to clock in and out the serial data on the si and so pins while being addressed by the csb. 13 si input spi data input the si input pin is used to receive seri al data into the device from the mcu. 14 vppref output vpp reference base drive base drive for external pnp pass transistor 15 gnd ground ground ground pin, return for all voltage supplies 16 so output spi data output the so output pin is used to transmit se rial data from the device to the mcu. 17 vcc supply vcc supply protected output 5.0 volt supply output for mcu vcc. this output supplies the vcc voltage for 5.0 volt mcus. it is short-circ uit and over-current protected. 18 vppsens input voltage sense from vpp feedback to internal v pp 6.5 volt regulator from external pass transistor 19 resetb output resetb output to mcu 5.0 v logic level reset signal used to reset the mcu during under and over- voltage conditions and for initial power-up, down and watchdog timeouts 20 vprot output sensor supply protected output the vprot output is a protected 5.0 volt output that tracks the v cc voltage but isolates the vcc output against sh orts to ground and to battery. it is intended to supply sensors which are located off of the ecu board. 21 lampout output warning lamp output low side driver output for mil (warning lamp) driven by spi input command 22 rgnd2 ground rout2 power ground ground connection for rout 2 low side driver. must be tied to vpwr ground. 23 rout2 output relay driver 2 output low side relay driver output # 2 driven by spi input command or rin2 logic input 24 n.c. no connect unused pin for future expansion 25 n.c. no connect unused pin for future expansion 26 tachout output tachometer output this pin provides the low side drive fo r a tachometer gauge or alternatively as a spi controlled low side driver, or oscillator output. 27 mrx output low side driver output output 5.0 v logic level iso9141 data to the mcu from the iso9141 in/out pin 28 mtx input iso9141 mcu data input input 5.0 v logic level iso9141 data from the mcu to the iso9141 in/out pin table 2. 33813 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 24 . pin pin name pin function formal name description
analog integrated circuit device data ? freescale semiconductor 7 33813 29 batsw output battery switch this output is a 5.0 v logic level that is high when keysw is high. it is only low when keysw is low. it can also be controlled via the spi. the batsw output may not be present in a different package but it?s function can be read by the spi. 31 injin1 input injector driver input 1 5.0 v logic level input from the mcu to cont rol the injector 1 driver output (can also be controlled via the spi) 33 ignin1 input ignition input 1 5.0 v logic level input from mcu controlling the ignition coil # 1 current flow and spark. (can also be controlled via the spi) 34 o2hin input o2 sensor heater input 5.0 v logic level input used to turn on and off the o2hout driver. the o2hout driver can also be turned on and off via the spi if this pin is not present in a different package. 35 rin2 input relay driver input 2 5.0 v logic level input from the mcu to control the relay 2 driver output rout2. the rout2 driver can also be turned on and off via the spi if this pin is not present in a different package. 36 rin1 input relay driver input 1 5.0 v logic level input from the mcu to control the relay 1 driver output rout1. the rout1 driver can also be turned on and off via the spi if this pin is not present in a different package. 37 keysw input key switch input the key switch input is a vpwr level si gnal that indicates that the key is inserted and turned to the on/off position. in the on position the (keysw = vbat) the ic is enabled and batsw = high (relay 2 on if programmed in spi). in the off position the ic is in sleep mode, only when the pwren bit in the spi register is also low. 38 injgnd2 ground injector driver ground ground connection for injector low side driver. must be tied to vpwr ground. 40 rgnd1 ground rout1 power ground ground connection for rout 1 low side driver. must be tied to vpwr ground. 41 rout1 output relay driver 1 output low side relay driver output # 1 driven by the spi input command or rin1 logic input 42 injgnd1 ground injector driver 1 ground ground connection for injector 1 low side driver. must be tied to vpwr ground. 43 injout1 output injector driver 1 output low side driver output for injector 1 driven by the spi input or by parallel input injin1 44 iso9141 input/output iso9141 k-line bidirectional serial data signal iso9141 pin is vpwr level in/out signal which is connected to an external ecu tester that uses the iso9141 prot ocol. the output is open drain and the input is a ratiometric vpwr level threshold comparator. 45 ignfb1 input feedback from collector 1 voltage feedback from collector of i gnition # 1 driver igbt through 10:1 voltage divider (9r:1r) 46 ignout1 output ignition output 1 output to gate of igbt or gpgd for ignition # 1 table 2. 33813 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 24 . pin pin name pin function formal name description
analog integrated circuit device data ? freescale semiconductor 8 33813 4 electrical characteristics 4.1 maximum ratings table 3. maximum ratings all voltages are with respect to ground, unless mentioned ot herwise. exceeding these ratings may cause malfunction or permanent device damage. parameter symbol min. max. unit electrical ratings v pwr supply voltage v pwr -0.3 45 v dc vpp supply voltage (if supplied externally and not using internal vpp regulator) v pp_ext -0.3 10.0 v dc v prot regulator v prot -0.3 v pwr v dc spi interface and logic input voltage (v si , v sclk , v csb , v rin1 , v rin2 , v injin1 , v ignin1 , v o2hin , v mtx ) v il , v ih -0.3 v cc v dc spi interface and logic output voltage (v so , v batsw, v mrx ,v vrsout ) v il , v ih -0.3 v cc v dc all low side drivers drain voltage (v injout1 , v rout1 , v rout2 , v lampout, v tachout ) v outx -0.3 v clamp v dc all pre-drivers output voltage (v ignout1 , v o2hout ) v gdx -0.3 10 v dc all pre-driver feedback inputs voltage (v ignfb1 , v o2hfb ) v gdfb -1.5 60 v dc all pre-driver current sense inputs voltage (v ignsensn , v ignsensp , v o2hsensn ,v o2hsensp ) v isens -0.3 1.0 v dc keysw input voltage (v keysw ) v keysw -18 v pwr v dc resetb output voltage (v resetb ) v resetb -0.3 v cc v dc iso9141 input/output voltage (v iso9141 ) v iso9141 -18 v pwr v dc output continuous current (injout1) ?t junction = 150 c i oc_injx ? 1.3 a output continuous current (rout1) ?t junction = 150 c i oc_r1 ? 2.0 a output continuous current (rout2) ?t junction = 150 c i oc_r2 ? 1.0 a output continuous current (lampout) ?t junction = 150 c i oc_lamp ? 1.0 a output continuous current (tachout) ?t junction = 150 c i oc_tach ? 50 ma maximum voltage for vrsn and vrsp inputs to ground v vrs_in -0.5 6.0 v dc maximum current for vrsn and vrsp inputs (internal diodes limit voltage) i v rsx_in ? 15 ma output clamp energy (injout1, rout1)(single pulse) ?t junction = 150 c, i out = 1.0 a e clamp tbd 100 mj output clamp energy (injout1)(continuous pulse) ?t junction = 125 c, i out = 1.0 a, tbd khz (max injector frequency is 70 hz) e clamp tbd tbd mj
analog integrated circuit device data ? freescale semiconductor 9 33813 electrical ratings (continued) vrs sensor input current range ? maximum current into vrsn pin or vrsp pin and ic ground i vrs_in -15 +15 ma thermal ratings operating temperature (automotive grade version) ? ambient ? junction ?case t a t j t c -40 -40 -40 125 150 125 ? c storage temperature t stg -55 150 ? c power dissipation (t a ? 25 ? c) p d ? 3.0 w peak package reflow temperature during reflow (4) , (5) t pprt ? note 5 c thermal resistance and package dissipation ratings thermal resistance ? junction-to-ambient (lqfp-48-ep package) (single layer board) ? junction-to-case (lqfp-48-ep package) r ? ja r ? jc 29 2.4 29 2.4 ? c/w notes 2. esd data available upon request. (items in red are not associated with any parameter) 3. esd1 testing is performed in accordance with the human b ody model (aec-q100-002) and the machine model (aec-q100-003). 4. pin soldering temperature limit is for 10 seconds maximum durat ion. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 5. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts (i.e. mc33xxxd enter 33xxx), and review parametrics. table 3. maximum ratings all voltages are with respect to ground, unless mentioned ot herwise. exceeding these ratings may cause malfunction or permanent device damage. parameter symbol min. max. unit
analog integrated circuit device data ? freescale semiconductor 10 33813 4.2 static electrical characteristics table 4. power input static electrical characteristics characteristics noted under conditions of 6.0 v ? v pwr ? 18 v, -40 ? c ? t c ? 125 ? c, and calibrated ti mers, unless otherwise noted. where applicable, typical values reflect the parameter?s approxim ate average value with v pwr = 13 v, t a = 25 ? c. characteristic symbol min typ max unit power input (vpwr) supply voltage (measured at vpwr pin) (6) ? logic stable range ? full operational range ? full parameter specification range v pwr ( fo ) v pwr ( fo ) v pwr ( fp ) 2.5 4.5 6.0 ? ? ? 45 36 18 v supply current ? all outputs disabled (normal mode). excludes base current to the external pno. i vpwr ( on ) ? 10.0 14.0 ma sleep state supply current (must have pwren & keysw ? 0.8 v for sleep state), ?v pwr = 18 v i v pwr (ss) ? 10 20 ? a v pwr over-voltage shutdown threshold voltage (ov reset) (7) v pwr(ov) 37.5 39 42 v v pwr over-voltage shutdown hysteresis voltage v pwr (ov-hys) 0.5 1.5 3.0 v v cc power on reset voltage threshold (por power on reset), rising v t v cc(por) 3.9 4.5 4.9 v v cc under-voltage shutdown threshold voltage (uv reset) (8) , falling v t v cc(uv) 2.9 3.7 3.9 v v cc por and under-voltage shutdown hysteresis voltage v cc(uv/por- hys) 100 ? ? mv v cc por and under-voltage non-overlap (por-uv) v cc, nonoverlap 0.8 1.0 1.2 v voltage pre- regulator output (vppref, vppsens) vppref output voltage (measured wi th vppref shorted to vppsens and no external output transistor) v ppref 5.85 6.5 7.15 v vppref output current (includes external pnp current) i vppref ? -5.0 ? ma vppref current limit (v pwr -v pp = 5.5 v t j = 25 c) i vppcl -5 -15 -20 ma output capacitance external (ceramic) v oce 2.2 ? 25 ? f vppsens input current (v pwr -v pp = 5.5 v t j =25 c) i vppsens ? ? 3.0 ma line regulation i vcc = 100 ma, i vprot = 50 ma 9.0 v< v pwr < 18 v and diodes inc. fzt753ta pnp regline_ vpp ? 2.0 25 mv dropout voltage (minimal input/output voltage, tracks input below) i vcc = 100 ma, i vprot = 50 ma and diodes inc. fzt753ta pnp v dropout_pp ? 1.05 1.4 v voltage regulator ou tputs (vcc, vprot) vcc output voltage 0 ? i vcc ?? i vcc_c 6.0 v< v pwr < 18 v v cc 4.9 5.0 5.1 v vcc output current continuous i vcc_c ? ? 200 ma notes 6. over-voltage thresholds minimu m and maximum include hysteresis. 7. under-voltage thresholds minimu m and maximum include hysteresis. 8. device is functional provided t j is less than 150 ? c. some table parameters may be out of specification.
analog integrated circuit device data ? freescale semiconductor 11 33813 voltage regulator outputs (vcc, vprot) (continued) vprot output voltage (tracks vcc) i vcc = 100 ma, i vprot = 50 ma 9.0 v< v pwr < 18 v | vcc -v prot | ? ? 20 mv vprot output current continuous i vprot_c ? ? 100 ma vcc output current limiting i vcc_cl 200 ? 500 ma vprot output current limiting i vprot_cl 110 ? 260 ma output capacitance external (v cc and v prot ) without reverse protection diode v oce 2.2 ? 47 ? f line regulation (both v cc and v prot ) i vcc =100 ma, i prot = 50 ma 9.0 v< v pwr < 18 v reg line_vb ? 2.0 25 mv load regulation (both vcc and vprot) measured from 10% to 90% of i vcc_c and i prot_c, v pwr = 13 v reg load_vb ? 2.0 25 mv dropout voltage (both v cc and v prot ) (minimal input/output voltage at full load, tracks input below) v dropout ? 1.05 1.4 v all low side drivers (inj1, rout1, rout2, lampout, tachout) output fault detection voltage threshold (9) outputs programmed off (open load) outputs programmed on (short to battery) v out (flt-th) 2.0 2.5 3.0 v output off open load detection current (inj1, relay1, relay2 & lamp) ?v drain = 18 v, outputs programmed off i (off)oco 40 75 115 ? a output off open load detection current tachout 10 ? 30 ? a output leakage current ?v drain = 24 v, open load detection disabled and output commanded off i out (lkg) ? ? 20 ? a over-temperature shutdown (ot) (10) t lim 155 ? 185 ? c over-temperature shutdown hysteresis (11) t lim (hys) 5.0 10 15 ? c output clamp voltage ?i d = 20 ma v oc 48 53 58 v injout1 drain-to-source on resistance ?i out = 1.0 a tj = 125 c, v pwr = 13 v ?i out = 1.0 a tj = 25 c, v pwr = 13 v ?i out = 1.0 a tj = -40 c, v pwr = 13 v r ds (on)_injx r ds (on)_injx r ds (on)_injx ? ? ? ? 0.4 ? 0.6 ? ? ? continuous current (not to exceed) i out(cc)_inj x ? ? 1.3 a output self limiting current i out (lim)_injx 1.6 ? 3.0 a notes 9. these parameters are guaranteed by design. production test equipment uses 1.0 mhz, 5.0 v spi interface. 10. this parameter is guaranteed by desi gn, however it is not production tested. 11. programmable via spi but vari able with magnitude input frequency table 4. power input static electrical characteristics characteristics noted under conditions of 6.0 v ? v pwr ? 18 v, -40 ? c ? t c ? 125 ? c, and calibrated ti mers, unless otherwise noted. where applicable, typical values reflect the parameter?s approxim ate average value with v pwr = 13 v, t a = 25 ? c. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 12 33813 rout1 driver drain-to-source on resistance ?i out = 700 ma, t j = 150 ? c, v pwr = 13 v r ds (on)_r1 ? 0.3 0.4 ? continuous current (not to exceed) i out(cc)_ r1 ? ? 2.0 a output self-limiting current (has inrush current timer) i out (lim)_r1 3.0 ? 6.0 a rout2 driver drain-to-source on resistance ?i out = 350 ma, t j = 150 ? c, v pwr = 13 v r ds (on)_r2 ? ? 1.5 continuous current (not to exceed) i out(cc)_r2 ? ? 1.0 output self-limiting current i out (lim)_r2 1.2 ? 2.4 lampout driver drain-to-source on resistance ?i out = 1.0 a, t j = 150 ? c, v pwr = 13 v r ds (on)_lamp ? ? 1.5 ? continuous current i out(cc)_lamp ? - 1.0 a output self-limiting current (has inrush current timer) i out (lim)_ lamp 1.2 ? 2.4 a tachout driver drain-to-source on resistance ?i out = 50 ma, t j = 150 ? c, v pwr = 13 v r ds (on)_tach ? ? 20 ? continuous current (not to exceed) i out(cc)_tach ? ? 50 ma output current shutdown i out (shutdo wn)_tach 60 ? 110 ma all pre-drivers (ignout1, and o2hout) pre-driver output voltage (typ ical values measured at v pwr = 13 v ?i gd = 500 ? a ?i gd = -500 ? a v gs(on) v gs(off) 4.8 0.0 8.0 0.375 9.0 0.5 v ignoutx output source current (ignout1 and ignout2 by default) ?@ 1.0 ?? v gd ?? 3.0, v pwr = 13 v i ign_gd_h 10 ? ? ma output off open load detection current ?v drain = 18 v, outputs programmed off i (off)oco 40 75 115 ? a gpgd output source current (o2hout by default) @ 1.0 ?? v gd ?? 3.0, v pwr = 13 v i gpgd_gd_h 10 ? ? ma output fault detection voltage threshold ? (for ignoutx at ignfbx pin not at input of 10:1 divider) ? (for 02hout @hfb pin) ?i gd = 500 ? a ?i gd = -500 ? a v ignfb (flt-th) v gpgd(flt_th) 100 1.0 250 2.5 400 4.0 mv v output clamp voltage v clamp 48 53 60 v table 4. power input static electrical characteristics characteristics noted under conditions of 6.0 v ? v pwr ? 18 v, -40 ? c ? t c ? 125 ? c, and calibrated ti mers, unless otherwise noted. where applicable, typical values reflect the parameter?s approxim ate average value with v pwr = 13 v, t a = 25 ? c. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 13 33813 all pre-drivers (ignout1, and o2hout) (continued) over-current voltage threshold (v o2hsensn to v o2hsensp ) v sens-th 180 200 220 mv over-current voltage threshold (v ignsensn to v ignsensp ) (ignin1 or ignin2 = 1) (v ignsensn to v ignsensp ) (ignin1 and ignin2 = 1) v sens-th v sens-th 180 360 200 400 220 440 mv current sense input offset current (ignsensp,ignsensn, o2h i sens-offset ? ? 15 ? a current sense input bias current i sens-bias ? ? 15 ? a iso-9141 transceiver parameters (8.0 v < v pwr < 18 v) input low voltage at iso i/o pin vil_iso ? ? 0.3xvpw r v input high voltage at iso i/o pin vih_iso 0.7*vpw r ? ? v input hysteresis at iso i/o pin vhyst_iso 0.15xvp wr ? ? v output low-voltage at iso i/o pin vol_iso ? ? 0.2xvpw r v output high-voltage at iso i/o pin voh_iso 0.8xvpw r ? ? v output current limit at iso i/o pin (mtx = 0) ilim_iso 50 100 150 ma load capacitance at iso i/o pin (13) cl_iso 0.01 3.0 10 nf output load current at iso i/o pin (mtx = 0, rload = 1.0 kw ??????? ) i_iso ? 12 ? ma vrs conditioner input comparator thresholds v vrs_thresh ? see table variable via spi or dynamically mv threshold accuracy ?steady state condition ( ? 20% only valid for vrs dac thresholds 110 mv and higher. all other thresholds guaranteed monotonic only.) accu thresh ? ? ? 20 % input bias current vrsp and vrsn (2.5 v common mode must be off) i biasrsx -5.0 ? 5.0 a vrs positive clamp voltage at i clamp = 10 ma v clamp_p 5.4 ? 6.0 v vrs negative clamp voltage at i clamp = 10 ma v clamp_n -0.44 ? -0.22 v notes 12. this parameter is guaranteed by desi gn, however it is not production tested. table 4. power input static electrical characteristics characteristics noted under conditions of 6.0 v ? v pwr ? 18 v, -40 ? c ? t c ? 125 ? c, and calibrated ti mers, unless otherwise noted. where applicable, typical values reflect the parameter?s approxim ate average value with v pwr = 13 v, t a = 25 ? c. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 14 33813 digital interface (mrx, mtx, csb, si, sclk, so, rinx, o2hin, injin1, ignin1, batsw, vrsout, resetb) input logic high-voltage thresholds (14) v ih 0.7 x v cc ? v cc + 0.3 v input logic low-voltage thresholds (14) v il gnd - 0.3 ? 0.2 x v cc v input logic voltage hysteresis (14) v hys 500 ? ? mv input logic capacitance (13) c in ? ? 20 pf sleep mode input logic current (14) ? keysw = 0 v i logic_ss -10 ? 10 ? a input logic pull-down current injin1, rin1, rin2, si, sclk,ignin1, o2hin ? 0.8 v to 5.0 v i logic_pd 30 50 100 ? a sclk input current ?v sclk = v cc i sclk -10 ? 10 ? a so tri-state output (in tri-state mode, csb = 1) ?0 v to 5.0 v i triso -10 ? 10 ? a csb input current ? csb = v cc i csb -10 ? 10 ? a input logic pull-up current - csb and mtx ? 0.0 to 4.2 v i logic_pj -30 -50 -100 ? a csb leakage current to v cc ? csb = 5.0 v, keysw = 0.0 v i csb(lkg) ? ? 10 ? a so, mrx high-state output voltage (csb =0 for so) ?i so-high = -1.0 ma v so_high v mrx_high v cc - 0.4 ? ? v so, mrx low-state output voltage (csb =0 for so) ?i so-low = 1.0 ma v so_low v mrx_high ? ? 0.4 v batsw high-state output voltage i so-high = -10 ma v batsw_high v cc - 1.0 ? ? v batsw low-state output voltage i so-low = 10 ma v batsw_low ? ? 1.0 v keysw high-state input voltage v keysw_high 4.5 - v pwr v keysw low-state input voltage v keysw_low -0.3 - 2.5 v keysw hysteresis v keysw_hys 100 ? ? mv vrs low-state output voltage ivrs-low= 1.0 ma v vrsout_low ? ? 0.4 v vrs low-state output voltage ivrs-low= 1.0 ma v vrsout_high v cc -0.4 ? 5.0 v reset low-state output voltage ireset-low= 1.0 ma v reset_low ? ? 0.4 v notes 13. this parameter is guaranteed by desi gn, however it is not production tested. 14. programmable via spi but vari able with magnitude input frequency. table 4. power input static electrical characteristics characteristics noted under conditions of 6.0 v ? v pwr ? 18 v, -40 ? c ? t c ? 125 ? c, and calibrated ti mers, unless otherwise noted. where applicable, typical values reflect the parameter?s approxim ate average value with v pwr = 13 v, t a = 25 ? c. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 15 33813 digital interface (mrx, mtx, csb, si, sclk, so, rinx, o2hin, injin1, ignin1, batsw , vrsout, resetb) (continued) reset high-state leakage voltage i reset_ leakage_high 10 ? 25 ? a reset pull-down resistor r reset_ puldown 200 ? 500 k ? table 4. power input static electrical characteristics characteristics noted under conditions of 6.0 v ? v pwr ? 18 v, -40 ? c ? t c ? 125 ? c, and calibrated ti mers, unless otherwise noted. where applicable, typical values reflect the parameter?s approxim ate average value with v pwr = 13 v, t a = 25 ? c. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 16 33813 4.3 dynamic electrical characteristics table 5. dynamic electri cal characteristics (15) characteristics noted u nder conditions of 6.0 v ? v pwr ? 18 v, -40 ? c ? t c ? 125 ? c, and calibrated timers, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with v pwr = 13 v, t a = 25 ? c. characteristic symbol min typ max unit power input required low state duration on v cc for power on reset ?v cc ? 0.2 v t reset 1.0 ? ? ? s power on reset pulse width t (por) 100 - - ? s watchdog timer maximum time value watchdog can be loaded with (default time) wdmax ? ? 10 sec. minimum time value watchdog can be loaded with wd min 1.0 ? ? ms reset pulse width when watchdog times out wd reset 100 ? ? ? s vrs conditioning input output blanking time programming range ? (% of previous out pulse 0 to 15/32 in 1/32 steps, 15/32 = 46.9%) output blank 0 ? 50 % output deglitch filter time (1/128 of the previous output pulse) output degli tch ? 1.0 ? % delay from csb to change in vrs comparator threshold - gbd delay thresh ? ? 10 ? s delay from csb to change in vrs output blank time - gbd delay obt ? ? 10 ? s iso9141 transceiver typical iso9141 data rate iso br ? 10 ? kbps turn off delay mtx input to iso output t txdf ? ? 2.0 ? s turn on/off delay iso input to mrx output t rxdf , t rxdr ? ? 1.0 ? s rise and fall time mrx output (measured from 10% to 90%) t rxr , t rxf ? ? 1.0 ? s maximum rise and fall time mtx input (measured from 10% to 90%) t txr , t txf ? ? 1.0 ? s all low side drivers output on current limit fault filter timer t sc1 30 60 90 s output retry timer t ref 7.0 10 13 ms inrush current delay timer t inrush 7.0 10 13 ms output off open circuit fault filter timer t (off)oc 100 ? 400 s output slew rate z load = 14 ?? and ? 10 mh ?? v load = 14 v t sr(rise) 1.0 5.0 10 v/ ? s output slew rate injout1, rout1, rout2 and lampout ?z load = 14 ?? and ? 10 mh, v load = 14 v t sr(fall) 1.0 5.0 10 v/ ? s propagation delay (input rising edge or csb to output falling edge) ? input at 50% v dd to output voltage 90% of v load (inj1, rout1, rout2, lamp) t phl ? 1.0 5.0 s propagation delay (input rising edge or csb to output falling edge) ? input at 50% v dd to output voltage 90% of v load (tachometer) t phl ? 1.0 6.0 s notes 15. these parameters are guaranteed by design. production test equipment uses 1.0 mhz, 5.0 v spi interface.
analog integrated circuit device data ? freescale semiconductor 17 33813 all low side drivers (continued) propagation delay (input falling edge or csb to output rising edge) ? input at 50%v dd to output voltage 10% of v load (inj1, rout1, rout2, lamp) t plh ? 1.0 5.0 s propagation delay (input rising edge or csb to output falling edge) ? input at 50%v dd to output voltage 10% of v load (tachometer) t plh ? 1.0 6.0 s output slew rate, tachout ?r load = 500 ??? v load = 14 v t sr(fall) 6.0 ? 14 v/ ? s all gate pre-driver (ign1 and o2h) output off open-circuit fault filter timer t (off)oc 100 ? 400 s over-current (short-circui t) fault filter timer t sc 30 ? 90 s propagation delay (input rising edge or csb to output rising edge) ? input at 50%v dd to output voltage 10% of v gs(on) t plh ? 1.0 5.0 s propagation delay (input falling edge or csb to output falling edge) ? input at 50%v dd to output voltage 90% of v gs(on) t phl ? 1.0 5.0 s spi digital interface timing (16) falling edge of csb to rising edge of sclk ? required setup time t lead 100 ? ? ns falling edge of sclk to rising edge of csb ? required setup time t lag 50 ? ? ns si to rising edge of sclk ? required setup time t si ( su ) 16 ? ? ns rising edge of sclk to si ? required hold time t si (hold) 20 ? ? ns si, csb, sclk signal rise time (17) t r (si) ? 5.0 ? ns si, csb, sclk signal fall time (17) t f (si) ? 5.0 ? ns time from falling edge of csb low-impedance (18) t so ( en ) ? ? 55 ns time from rising edge off csb to so high-impedance (19) t so ( dis ) ? ? 55 ns time from falling edge of sclk to so data valid (20) t valid ? 25 55 ns sequential transfer rate ? time required between data transfers t str ? ? 1.0 s notes 16. these parameters are guaranteed by design. production test equipment uses 1.0 mhz, 5.0 v spi interface. 17. rise and fall time of incoming si, csb, and sclk signals sugges ted for design consideration to prevent occurrence of double pulsing. 18. time required for valid output status data to be available on so pin. 19. time required for output states data to be terminated at so pin. 20. time required to obtain valid data out from so following the fall of sclk with 200 pf load. table 5. dynamic elec trical characteristics (15) characteristics noted under conditions of 6.0 v ? v pwr ? 18 v, -40 ? c ? t c ? 125 ? c, and calibrated timers, unless otherwise noted. where applicable, typical values reflect the parameter?s approximate average value with v pwr = 13 v, t a = 25 ? c. characteristic symbol min typ max unit
analog integrated circuit device data ? freescale semiconductor 18 33813 4.4 timing diagrams figure 4. timing diagram 4.5 typical electrical characteristics figure 5. i pwr vs. temperature t so(dis) 0.7 v dd 0.2 v dd 0.2 v dd 0.7 v dd 0.2 v dd t lead t so(en) t si(su) t si(hold) t valid t lag csb sclk si so msb in msb out lsb out 0.7 v dd 0.2 v dd 0 25 50 100 125 -40 75 -25 i pwr current into v pwr pin (ma) 14 15 16 17 18 19 20 t a, ambient temperature ( ? c) v pwr @ 18 v
analog integrated circuit device data ? freescale semiconductor 19 33813 figure 6. sleep state i pwr vs. temperature figure 7. sleep state i pwr vs. v pwr figure 8. r ds(on) vs. temperature at 1.0 a 0 25 50 100 125 -40 75 -25 sleep state i pwr versus temperature i pwr current into v pwr pin (ua) 2 4 6 8 10 12 14 t abi tt t 0 25 50 100 125 -40 75 -25 i pwr current into v pwr pin (a) 1 2 3 4 5 6 7 t a, ambient temperature ( ? c) v pwr @ 13 v 5 10152025 0 i pwr current into v pwr pin (a) 20 40 60 80 100 120 140 v pwr t a = 25 ? c 02550 100125 -40 75 -25 75 100 125 150 175 200 t a, ambient temperature ( ? c) v pwr @ 13 v r ds(on) (mohm) 50
analog integrated circuit device data ? freescale semiconductor 20 33813 figure 9. open load detection current at threshold figure 10. open load detection threshold vs. temperature figure 11. open load detection current 02550 100125 -40 75 -25 i oco, open load (a) 20 40 60 80 100 120 140 t a, ambient temperature ( ? c) v pwr @ 13 v 02550 100125 -40 75 -25 v out(flt-th), open load threshold (v) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a, ambient temperature ( ? c) v pwr @ 13 v 02550 100125 -40 75 -25 i oco, open load (a) 20 40 60 80 100 120 140 t a, ambient temperature ( ? c) v pwr @ 13 v
analog integrated circuit device data ? freescale semiconductor 21 33813 figure 12. open load detection threshold vs. temperature figure 13. recommended circuit to use batsw as an led driver 02550 100125 -40 75 -25 v out(flt-th), open load threshold (v) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a, ambient temperature ( ? c) v pwr @ 13 v 300 offboard mc33814 300 batsw led .01f gnd
analog integrated circuit device data ? freescale semiconductor 22 33813 \ figure 14. typical el ectrical specifications 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 100ua 500ua 1ma iload gate ? pre \ drive ? voh ? vs ? vpwr ?? @ ? 25 ? deg ? c 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0 5 10 15 20 100ua 500ua 1ma vpwr ?? (v) gate ? pre \ drive ? vol ? vs ? vpwr ?? @ ? 25 ? deg ? c
analog integrated circuit device data ? freescale semiconductor 23 33813 figure 15. typical electrical specifications (continued) 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 4.4 4.6 4.8 5 5.2 5.4 5.6 0ma 50ma 100ma vpwr ?? (v) v p r o t ? ( v ) vprot ? vs ? vpwr ?? @ ? 25 ? deg ? c iload 4 4.2 4.4 4.6 4.8 5 5.2 44.555.56 50ma 100ma 200ma vcc ? vs ? vpwr ?? @ ? 25 ? deg ? c 0.15 0.17 0.19 0.21 0.23 0.25 0.27 4 6 8 10 12 14 inj ? driver ? rdson ? vs ? vpwr ?? 25 ? deg ? c vpwr ?? (v) r d s o n ? ( o h m s )
analog integrated circuit device data ? freescale semiconductor 24 33813 5 general ic functional de scription and application information 5.1 functional pin description 5.1.1 vpwr supply input the v pwr pin is the battery input to the 33813 ic. the v pwr pin requires external reverse battery and adequate transient voltage protection. all ic analog current and internal logic current is provided from the v pwr pin. an over-voltage comparator monitors this pin and when an ov er-voltage condition is present all outputs and voltage regulators are shut off for protection. the vpwr pin should be bypassed to ground, as close to the ic as possible, with a 0.1 f ceramic capacitor. 5.1.2 vppref output the vppref output pi n is used to drive the base of an external regulator pnp pass tr ansistor. the output of this v pp regulator supplies the input voltage to the two internal 5.0 volt regulators. the v pp regulator is a low drop-out (ldo) regulator that provides a regulated output voltage when the input is greater than its s pecified voltage level, and follows the input voltage when it is below its specified voltage level. it is not recommended that this vo ltage be brought off of the module pc board, because it may not have adequate protection to prevent damage to the pnp pass transistor under shor t-to-ground or short-to-battery conditions. 5.1.3 vppsens input the vppsens pin is used to monitor the v pp pre-regulator output voltage from the external pass transistor?s collector, and to supply the input voltage to the v cc and v prot regulators. the vppsens pin should be bypassed to ground, as close to the ic as possible, with a 0.1 f ceramic capacitor and a higher value electrolytic capacitor in parallel. 5.1.4 vcc output (5.0 v supply) the vcc regulator obtains its input voltage from the vpp pre-regu lator. the vcc output supplies 5.0 v power to the system mcu and other on-board peripherals. a power on reset (por) circuit monitors the v cc output voltage level. when the v cc voltage exceeds the v cc(por) threshold, the resetb line is held low fo r an additional delay time, t (por) , and then brought to a logic one level. an under-voltage (uv) circuit monitors the output of the v cc regulator and when the voltage goes below the v cc(uv) threshold for more than the v cc filter time, t (vcc-uv) , the resetb line is asserted to a logic ze ro state and remains there until the por condition is met. 5.1.5 vprot output (5.0 v protected supply) the vprot regulator obtains its in put voltage from the v pp pre-regulator and its reference voltage from the vcc output. vprot tracks v cc and is protected against shorts to ground, shorts to battery, over-curr ent and over-temperature. the vprot output supplies 5.0 v power to any external sensors and other off-board peripherals. the v prot regulator on/off state can be controlled via a bit in the spi control registers. the vprot out put should be protected against esd by means of a 0.1 f ceramic capacitor on the output and a higher va lue electrolytic capacitor in parallel.
analog integrated circuit device data ? freescale semiconductor 25 33813 5.1.6 gnd the gnd pin provides the ground reference for the v pwr, v pp, v prot and v cc supplies. the gnd pin is used as a return for both the power supplies as well as power ground for some of the lower current output drivers. t he higher current output drivers have their own ground pins. all ground pins (injgnd1, injgnd2 , rgnd1, and rgnd2) and the ex posed pad must be directly connected to this pin and the negative bat tery terminal. there is no separate ground pin associated with the lampout driver, it shares a ground with rout2. 5.1.7 sclk input the serial clock (sclk) pin clocks the internal spi shift regist er of the 33813. the si data is latched into the input shift re gister on the rising edge of sclk signal. the so pi n shifts status bits out on the falling edg e of sclk. the so data is available for the mcu to read on the rising edge of sclk. with csb in a logic high state, signals on the sclk and si pins will be ignored and the so pin will be in a high-impedance state. the sclk signal consis ts of a 50% duty cycle with cmos logic levels referenced to v cc . all spi transfers consist of exactly 16 sclk pulses. if any more or less than 16 clock pulses are received within one frame of csb going low and then high, a spi error is reported in the spi status register. the spi error bit will also be set whenever an invalid spi message is received, even though it may contain 16-bits. 5.1.8 csb input the system mcu selects which slave is 33813 to receive spi co mmunication using separate chip select (csb) pins. with the csb in a logic low state, spi words may be sent to the 33813 via the serial input (si) pin, and st atus information is received by the mcu via the serial output (so) pin. t he falling edge of csb enables the so output a nd transfers status information into the so buffer. the rising edge of the csb initiates the following operation: 1. disables the so driver (high-impedance) 2. activates the received command word, allowing the 33813 to activate/deactivate output drivers. to avoid any spurious data, it is essentia l that the high-to-low and low-to-high transitions of the csb signal occur only when sclk is in a logic low state. internal to the 33813 device is an active pull-up to v cc on csb. in cases where voltage exists on csb without the application of v cc , no current will flow from csb to the vcc pin. th is input requires cmos logic levels referenced to v cc and has an internal active pull-up current source. 5.1.9 si input the si pin is used for serial instruction data input. si informati on is latched into the input regi ster on the rising edge of s clk and the input data transitions on the falling edge of sc lk. a logic high state presen t on si will program a one in the command word on the rising edge of the csb signal. to program a complete word, 16 bits of information must be ent ered into the device. this input requires cmos logic levels referenced to v cc . 5.1.10 so output the so pin is the output from the spi shif t register. the so pin remains high-imped ance until the csb pin transitions to a logi c low state. all normal operating drivers are reported as zero, all faulte d drivers are reported as one. the negative transition of csb enables the so driver. the si / so shifting of the data follows a first-in -first-out protocol, with both input and out put words transferring the most significa nt bit (msb) first. the serial output data is available to be latched by the mcu on the rising edge of sclk. the so data transitions on falling edg e of the sclk. this output provides cmos logic levels referenced to v cc.
analog integrated circuit device data ? freescale semiconductor 26 33813 5.1.11 keysw input keysw is the input from the vehicle igni tion keyswitch. this signal is at v bat (12 v) when the key is inserted and turned to the on position. when the key is in the off position and/or remove d from the keyswitch, this input is pulled to ground by an intern al pull-down resistor. when this signal is low, and the pwren spi c ontrol register bit is also low, the 33813 is in the sleep mode . if the pwren spi control register bit is logic one, when the keysw goes low, only the outputs are tu rned off (except rout2 if the shut down disable bit is set). when the pwren spi control re gister bit also goes to zero, the entire circuit enters sleep mode. when keysw signal goes high, it wakes up the ic, turns on the v pp regulator and a power on reset signal is generated. this pin is internally protected against a re verse battery condition by an internal diode. the state of the keysw input is also avail able as a bit in the spi status register. 5.1.12 pwren spi control register bit the pwren signal is a bit in the spi control register th at, along with keysw, batsw, and the rout2 output can provide the power start-up logic of the vehicle. the purpose of the pw ren signal is allow the mcu to cont rol the shutdown of power to itself when the user turns off the keysw. this may be necessary to allow the mcu the time required to perform its pre-shutdown routines. when the mcu wants to shutdown the power supplies in the 33813, it must write a logic zero (0) to the pwren bit in the spi control register. only the state of the pwren bit in the spi control register will control the shutdown of the 33813 power supplies. 5.1.13 batsw output the batsw output pin is a 5.0 v logic level output that by default is an indicati on of the state of th e keysw input. when keysw is at v bat (12 v) level the batsw output is a logic 1 (5.0 v), and when keysw is at ground (0 v) level, batsw is at a logic 0. the batsw output may be used to inform the mcu that the user is trying to shutdown the vehicle. the batsw output can also be used to control an ls driver, such as the relay 2 driver, by co nnecting the batsw output to the rin2 input. in certain packaged options of t he 33813, the batsw signal is not brought out to a pin. in this case, the batsw signal can stil l be determined by the mcu by reading the state of batsw bit in the spi status register. the m cu can then control the rout2 (relay 2 output) by setting the ?rin 2? bit in the spi control register. if the batsw signal is not needed by the mc u or to control the relay 2 output, it can also be configured as a low current led high side driver controlled through the spi interface. as a high side driver, batsw can also be pwm?d to allow an led to be dimmed. a bit in the spi battery switch logic output configur ation register called ?hsd?, controls whether the batsw output will be a simple high side driver, or will be controlled by keysw as indicated above. if the batsw output is used to control an led, the led cathode should be tied to ground and the led anode should be connected to the batsw pin through an external resistor . the value of the external resistor should be 340 ohms or greater. care must be taken if the batsw output is sent off-board due to the chance of shorts to th e battery or shorts to ground, for which t he output is not protect ed. at a minimum, this output should be protected by a diode, the current limit resistor, and an esd capac itor (0.01 f ceramic). 5.1.14 using rout2 as a power relay the rout2 (relay 2 output) can be used to drive a power relay. the rin2 input or the rin2 bit in the spi control register can be used to turn the rout2 output on or off as desired. the batsw output can be connected to the rin2 input to control the power relay, or the mcu can chose to c ontrol the rin2 bit in the spi control register to actuate the power relay. the rout2 output is unique in that it can be kept turned on even after keysw is turned off (as long as the pwren bit is still set to a one) by setting the shut down disable (sdd) bit in the rout2 configuration register.
analog integrated circuit device data ? freescale semiconductor 27 33813 5.1.15 iso9141 transceive r (mtx, mrx, iso9141) these three pins are used to provide an iso914, k-line commu nication link for the mcu to provide diagnostic support tachout output for the system. mrx is the 5.0 v logic level serial output line to the mcu. mtx is the 5.0 v logic level serial input to the ic from the mcu. the iso9141 pin is a bi -directional line, consistent with the iso9141 specificat ion for signalling to and from the mcu. there is only one bit in the spi status register to indicate an over-temperature fault from the iso9141 functional blo ck. there are no configuration or control registers associated with this functional block. 5.1.16 tachometer (tachout) the tachout pin is a low side driver, that can used to driv e a tachometer meter movement. tachout can be programmed via the spi to: 1. output the same signal as vrsout divided by a 1 to 32 programmable divider, 2. output a pwm signal wit h a frequency and duty cycle programmable via the spi, or 3. output one of 8 fixed frequencies as indicated in table 6 . if a tachometer is not required the tachout output can also be used as a low current, spi controlled, low side driver to drive a led or other low current load. the spi co nfiguration register for t he tachometer is used to de termine which mode this output will be used in. the tachout output handles over-current (oc) diff erently than the other low side drivers. when an over-current limit is reached the tachout output does not enter a current limiting stat e but rather shuts the outp ut off to protect the outp ut device. the retry option works similarly to the other low side drivers. in the lsd mode bit 4 of the spi configuration register controls the turn on or turn off of the open load detect current sink. table 6. tachout spi configuration register spi configuration register 4 bits 6, 5 tachout mode 00 (default) vrsout divided by ?n? where ?n? is defined by bits 0 thru 4 of spi configuration register 4 (1 - 32) 00001 = 1 (default) . 11111 = 31 00000=32 01 oscillator output 10 low side driver (lsd) 11 same as 10 above table 7. tachout spi configuration register spi configuration register bits 2,1,0 oscillator frequencies 000 (default) 10 hz 001 100 hz 010 1.0 khz 011 5.0 khz 100 10 khz 101 20 khz 110 40 khz 111 100 khz (not recommended for use)
analog integrated circuit device data ? freescale semiconductor 28 33813 5.1.17 injin1 input the injin pin is the parallel inputs that co ntrols the injector output injout1. the in jin1 pin is logic le vel inputs with a bui lt-in pull-down to ground to prevent accidental ac tuation if the connection to the pin is lo st. as a default, injin1 input is ored wi th the injector control bit in the spi on/off control word. this is to allow the injout1 to be controlled by either the injin or v ia the spi when either injector driver is bein g used for purposes other than injector drive. 5.1.18 injout1 driver outputs this output pin is the injector driver ou tputs for the one injector that the ic s upports. if an injector is not needed, one inj out1 can be used as a general purpose low side driver for relays, moto rs, lamps, gauges, etc. the injector driver outputs can be controlled by the parallel input (i njin1) or the appropriate bit in the spi inje ctor command register. th e injector output can also be pwm?d via the spi for use as variable speed motor drivers, le d/lamp dimming drivers, or as a fuel pump driver. the injector output is forced off dur ing all reset events. 5.1.19 rin1, rin2 inputs the rin1 and rin2 pins are the parallel inputs that control the relay outputs, ro ut1 and rout2 respectively. the rin1 and rin2 pins are 5.0 v logic level inputs with built-in pull-downs to ground to prevent accidental actuation of a relay if the connection to the pin is lost. as a default, rin1 and rin2 inputs are ored with the relay c ontrol bits in the spi on/off control word. thi s is to allow the rout?s to be controlled by either the rin?s (parallel inputs) or via t he spi when either relay driver is being used for purposes other than relay drive. 5.1.20 rout1, rout2 driver outputs these are output pins for rout1 and rout2 low side drivers. these outputs have differ ent current ratings and can be used to drive relays or other inductive loads. each output is controll ed via the spi or via the rinx l ogic inputs. each output has a pu ll- down current sink that can be enabled via the spi to provide op en load diagnostics. the open load detect current sink can be disabled via the spi to allow the outputs to be used as led dr ivers. the routx outputs can also be pwm?d via the spi for use as variable speed motor drivers, led/lamp dimming drivers, or as a fuel pump driver (rout1). all control and configuration for the rout?s is via the spi rout1 and rout2 on/off word in the spi control register and the individual rout1 and rout2 words in the spi control register. the rout2 relay output can be configured in spi to drive a power relay controlled by the batsw signal. 5.1.21 lampout driver output the lamp driver output, lampout is a low side driver capable of driving an incandescent lamp. the current limit contains a programmable delay to allow the driver to handle the inrush curr ent of a cold lamp filament. a pull-down current sink is provid ed to allow the ic to detect when the bulb is burned out (open fila ment). the turn on and off of the lamp is via the spi on/off control register word and it also has the ability to be pwm?d for advanced diagnostic (dimming) purposes via the spi lamp control register. the output can also be used to drive a led if the open load detect current sink is commanded off via the spi, to prevent ?ghosting?. the lampout spi configur ation register contains the following bits. table 8. tachout spi configuration register 7 6 5 4 3 2 1 0 retry enable (0) v rsout /lsd (0) v rsout / osc. mode (0) ol current sink enable (0) ?n 16 in- rush delay (0) ?n 8 output freq. 2 (0) ?n 4 output/pwm freq. 1 (0) ?n 2 output/pwm freq. 0 (1) ?n 1
analog integrated circuit device data ? freescale semiconductor 29 33813 the retry enable bit, bit 7, when set will allow the output to turn on for a short period and off for a long period when an ove r- current condition is present. the open load (ol) current sink disable allow the current sink to be turned off when using the dr iver as an led driver to prevent ghos ting, where the leds appears to be partially on du e to the ol current sink. it can also be turn ed off to measure the output device leakage. the inrush delay bit, when set (by default for the lamp driver) waits an additional t ime before annunciating an over-curr ent condition. this is done to allow for the in rush current of an incandescent lamp. the intern al pwm duty cycles (d/c) are controlled by the lower 7 bits in the corresponding spi control register. the external duty cycles ar e provided by the mcu on the input pin of the corresponding output driver. 5.1.22 vrsp, vrsn inputs, vrsout output the 33813 contains a vrs input conditioning circuit that empl oys a differential input. vrsp and vrsn are the positive and negative inputs from the vrs. (see diagram on next page) internal zener diode clamps to ground and v cc limit the input voltage to within the safe operating range of the ci rcuit. it is important to provide external 15 k current limiting resistors to prevent damage to the vrsp and vrsn inputs. (see r1 and r2 below) the vrs circuit conditions and digitizes the input from the crankshaft mounted toothed wheel to provide an angle clock and rpm data to the mcu. this circuit provides a comparator with multiple thresholds, which are programmed via the spi to allow the vrs circuit to handle different sensors and the wide dynamic range of the vrs output at engine speeds from crank to running. the output of this circuit is provided on the vrsout pin, which is a 5.0 volt logic level signal to the mcu. the comparator threshold values can also be controlled aut omatically based on the input signal amplitude. the output of the comparat or contains a programmable one shot, noise blanking circuit. the time value of this blanking pulse can be selected via the spi as a percentage of the last input high (o r low) pulse. the vrsout output can also be divided and sent to the tach out pin to drive a tachometer. table 9. lampout spi configuration register 7 6 5 4 3 2 1 0 retry enable (0) x (0) x (0) ol current sink enable (1) in- rush delay (1) x (0) pwm freq. 1 (0) pwm freq. 0 (0) table 10. pwm duty cycles bits 1, 0 pwm frequency pwm d/c 00 none or on ext. pin none or on ext. pin 01 100 hz internal 10 1.0 khz internal 11 on ext pin : 100 internal table 11. spi vrs manual configuration register spi vrs manual parameters configuration register bits 7, 6, 5, 4 threshold values (nominal) 0000 0.01 - 28 mv (tolerance not specified below 110 mv threshold. only specified for monotonicity.) 0001 0.01 - 36 mv (tolerance not specified below 110 mv threshold. only specified for monotonicity.) 0010 3.0 - 36 mv (tolerance not specified below 110 mv threshold. only specified for monotonicity.) 0011 8.0 - 48 mv (tolerance not specified below 110 mv threshold. only specified for monotonicity.)
analog integrated circuit device data ? freescale semiconductor 30 33813 5.1.23 controls for the vrsn and vrsp inputs the vrs can be connected to the 33813 in either a differential or single-ended fashion. the use of differential filtering capac itor, and grounded capacitors of at least 100 nf are also advisable. in some applications, a damping resistor of approximately 5.0 kohm directly across the pickup coil is also useful to minimize high frequency ringing. 5.1.24 gnd vrsn bit to use the vrs inputs in a single-ended co nfiguration the ?gnd vrsn? bit in the spi co nfiguration register must be set to indi - cate to the 33813 that this mode is being used. the vrs is then connected between the vrsp input and ground. the default for this bit is zero (0) indicating that the differential mode is selected. 5.1.25 2.5 volt reference disconnect bit the disconnect 2.5 volt reference bit in the spi vrs configuration register is used to disconnect the internal 2.5 volt reference signal from the vrsn and vrsp inputs, so that an external refere nce voltage can be employed. the default state of this bit is zero (0), indicating that the internal 2.5 volt reference voltage is connected to the vrsn and vrsp inputs. 5.1.26 selecting the input th reshold and blanking time two different spi registers are provided to control the vrs circuit values in the m anual mode. the spi vrs configuration regist er is used to set the ?engine running? values for the threshold and bl anking filter and the spi vrs c ontrol register is used to pr ovide the ?engine cranking ?threshold and blanking filter values. once the engine is runni ng, the mcu clears the spi vrs control register and the 33813 will use the values fo und in the spi vrs configuration register. 0100 23 - 55 mv (tolerance not specified below 110 mv threshold. only specified for monotonicity.) 0101 (default) 35 - 75 mv (tolerance not specified below 110 mv threshold. only specified for monotonicity.) 0110 74 mv (tolerance not specified below 110 mv threshold. only specified for monotonicity.) 0111 110 mv - 1.715 v +/- 20% 1000 150 mv +/- 20% 1001 215 mv +/- 20% 1010 300 mv +/- 20% 1011 425 mv +/- 20% 1100 600 mv +/- 20% 1101 850 mv +/- 20% 1110 1.210 v +/- 20% 1111 1.715 v +/- 20% table 11. spi vrs manual configuration register spi vrs manual parameters configuration register bits 7, 6, 5, 4 threshold values (nominal)
analog integrated circuit device data ? freescale semiconductor 31 33813 5.1.27 input comparator threshold values the threshold voltage for the input comparator is produced by a 4-bit d/a converter. th e control of the d/a output value is by means of the upper four bits of the spi vr s configuration register or the upper four bits of the spi vrs control register. when the contents of the spi vrs contro l register contains all zeros, the binary value for the d/a threshold is taken from the value in the spi vrs configuration register. when the contents of the spi vrs control register is non-zero, then the value in the upper four bits of the spi vrs control register is used to set the d/a output. the values outputted by this d/a, using either the spi vrs control register or the spi vrs co nfiguration register, are listed in table 11 in the threshold values t able. the blanking one-shot time is also set via the lower 4 bits of the spi vrs configurat ion register or the spi vrs cont rol register using the same cond ition, as described previously for the threshold d/a. 5.1.28 blanking time definitions the values for the one shot blanking, as a percentage of the last high output pulse period is shown in table 12 . 5.1.29 manual and automatic modes the spi vrs miscellaneous configuration register has a bit to enable the automatic select ion of the comparator threshold (bit 7 ). at this time, the operation of automatic mode remains tbd . 5.1.30 vrs peak detector the vrs peak detector determines the magnitude of the positive pe ak of the vrs input signal and digitizes it. the value of the vrs peak voltage is reported in the vrs spi st atus register bits 7, 6, 5, and 4. the mcu can read t he value of peak voltage aft er the zero crossing time of the input pulse, and uses this information to set the threshold and blanking parameters for subsequen t input pulses. status bits reflect t he last detected peak and only read 0000 after a por or spi reset command. table 12. spi vrs manual configuration register spi vrs configuratio n/control register bits 3,2,1,0 blanking time in% (of last pulse high period) 0000 (default) 0.0 0001 3.12 0010 6.25 0011 9.37 0100 12.5 0101 15.62 0110 18.75 0111 21.87 1000 25 1001 28.1 1010 31.3 1011 34.4 1100 37.5 1101 40.6 1110 43.8 1111 46.9
analog integrated circuit device data ? freescale semiconductor 32 33813 5.1.31 vrs deglitching filters the vrs input circuit has additional filter s on the rising and falling edges of the input waveforms to reduce the effect of sho rt transitions that may occur during those nois e sensitive times. the deglitching filters are approximately 1% of the last positiv e pulse period. the deglitch filters are enabled by setting the deglitch bit (bit 3) in the spi vrs miscellaneous parameters configuration register. this bit is, by default, zero (0), meaning that the deglit ch filters are disabled. 5.1.32 high/low reference bit the high/low reference bit in the spi vrs mi scellaneous configuration register is used to change the use of the input high puls e timing to input low pulse timing, in cases where an elongated toot h wheel is being used rather than the missing tooth wheel. th e default for this bit is zero (0), indicating the us e of a crankshaft wheel with a missing tooth (or teeth). 5.1.33 disable vrs bit the disable vrs bit in the spi vrs miscellaneous configuration re gister is used to disable the vrs input circuitry when there i s no need for a vrs input conditioning circuit. this would be the ca se, for example, if the crankshaft wheel sensor was a hall ef fect device whose output could be directly input to the mcu. the default for this bit is zero (0) indicating that the vrs input conditioning circuitry is active. table 13. peak detector output in spi vrs st atus register spi vrs status register bits 7,6,5,4 peak values (nominal) 0000 (default) 10 mv 0001 14 mv 0010 20 mv 0011 28 mv 0100 40 mv 0101 56 mv 0110 80 mv 0111 113 mv 1000 159 mv 1001 225 mv 1010 318 mv 1011 450 mv 1100 636 mv 1101 900 mv 1110 1.273 v 1111 1.800 v
analog integrated circuit device data ? freescale semiconductor 33 33813 5.1.34 clamp active status bits there are two clamp active status bits in the spi vrs status re gister. one is for the low pulse clamp and the other is for the high pulse clamp. when either of these bits ar e a one (1), it indicates that the peak vo ltage for that part of the input waveform ha s exceeded the clamp voltage and is being clamped to the high or low voltage limit. these status bits can be used to indicate tha t the engine has attained the speed necessary to switch from ?cr anking? values for the threshold and blanking (in the spi vrs control register) to the ?running? values. (in the spi vrs configuration register). 5.1.35 pre-driver operation there are three identical pre-drivers in the 33813. each pre-driver can be configured as either an ignition (igbt) pre-driver o r a general purpose gate driver (gpg d). by default, one pre-driver is configured as a gpgd (o2hout) and two pre-drivers are configured as ignition (ignout1) pre-drivers. a bit in each of the spi configuration registers, for each pre- driver, defines whether the pre-driver behaves as an ignition or a gpgd pre-driver. it should be noted that there are only two current measur ement circuits, isgnsensp/n and o2 sensp/n. when both pre-drivers are used as gpgd, then ignsensp/n is as sociated with the ignout1 pre-driver only , and the o2sensp/n is associated with the o2out pre-driver. 5.1.36 o2hin input the o2hin pin is the parallel input that controls the o2ho ut pre-driver output. the o2hin pin is a 5.0 v logic level input with a built-in pull-down to ground to prevent accid ental actuation of the pre-dr iver output if the connection to the pin is lost. as a default, the o2hin input is ored with the o2hout control bit in the spi on/off control wo rd. this is to allow the o2hout to be controlled by either the o2hin (p arallel input) or via the spi. 5.1.37 o2hout pre-driver output with drain feedback input o2hfb the o2hout output is a pre-driv er output that controls the ga te of a mosfet to drive a heate r on an o2 (lamda) sensor. the pre-driver is capable of driv ing most power mosfets. the o2hout output and associated drain feedback pin o2hfb provide short to battery, over-current protection for the external driver mosfet. more accurate current control can be provided by plac ing a current sense resistor between the o2sensp and o2sensn pins. output-off open circuit (ol) and outpu t-on over-current (oc) faults ar e detected and annunciated via the spi. 5.1.38 ignin1 input the ignin1 pin is the parallel inputs that control the ignout1 pre-driver output. the igni n1 pin is a 5.0 v logic level input with a built-in pull-down to ground to prevent accidental actuation of a pre-driver output if the conn ection to the pin is lost. as a default, the ignin1 input is ored with th e ignout1 control bit in the spi on/off contro l word. this is to allow the ignout1 to be controlled by either the ignin1 (parallel input) or via the spi. 5.1.39 ignout1 pre-driver output, with feedback ignfb1 and current sense inputs the ignout1 output is a pre-driver output that drives an igbt that controls t he ignition coil current to produce a spark. the ignout1 output and its feedback pins ignfb1 provide short to battery and one shared current s ense resistor provides over- current protection for the ex ternal driver transistors. when us ed as an igbt driver, a 10:1 voltage divider (9r:1r) must be use d on the feedback pins to prevent the 400 volt flyback from damaging the ic. if two ignition pre-drivers are not requir ed, they can be reconfigured, via the spi, as general pu rpose gate drivers (gpgds) us ed to drive ordinary mosfets.
analog integrated circuit device data ? freescale semiconductor 34 33813 more accurate current control can be provided by placing a cu rrent sense resistor between the ignsensp and ignsensn pins. when both pre-drivers are used as ignition (igbt) pre-drivers, the both pre-drivers can share one current sense resistor. the input controls will determine the value of the current sense th reshold voltage across the current sense resistor. when either o ne of the inputs is on, the threshold voltage will be v sens-th , but when both inputs are on simultaneously, the threshold will be raised to 2v sens-th to compensate for both pre-drivers being on. 5.1.40 resetb the resetb pin is a 5.0 volt logic, low level output that is used to rese t the mcu. the resetb pi n is an open drain output. without power on the 33813 circuit, the resetb pi n is held low by an internal pull-down resistor. in a typical application, the resetb pin must be pulled up extern ally by a pull-up resistor to vcc ?? when power is applied to the circuit and the voltage on the vcc pin reaches the lower voltage threshold, the resetb pin will remain at a low level (open drain fet turned on) for a period of time equal to the time value wd reset . after this time period, the resetb pin will go high and stay high until a reset pulse is generated due to any of the following events: 1. a watchdog timer timeout event occurs, 2. an under-voltage event on vcc occurs, or 3. an over-voltage event on vpwr occurs. a power on reset (por) is always provided upon power on (i .e. anytime the ic goes from sl eep state to active state). 5.1.41 disabling the watchdog timer since a watchdog reset occurs, by default 10 seconds after the por, if the mcu needs to programmed in-circuit, a means of disabling the watchdog must be provided to avoid interrupti ng the mcu programming procedure. this disable mechanism can be a jumper between the resetb pin of the 33813 and the mcu?s re set input pin, or via an isolation resistor placed between the resetb pin on the 33813 and the mcu?s rese t input pin that allows the mcu?s rese t pin to be pulled high independently of the 33813 resetb. the watchdog can also be disabl ed via a bit in the spi wd configuratio n register. 5.1.42 internal reset there is a bit in the spi control register that is labelled ?reset?. when this bit is set to a one (1) by the mcu, it will inst ruct the 33813 to perform an internal reset. this reset will not toggle the resetb output pin, but will cause all internal registers to be initialized back to their default values, including cl earing the reset bit in the spi control register. 5.2 mcu spi interface description the 33813 device directly interfaces to a 5.0 v micro controller unit (mcu) using a 16-bit serial peripheral interface (spi) protocol. spi serial clock frequencies up to 8.0 mhz may be used when programming and reading output status information (production tested at 1.0 mhz). figure 16 illustrates the spi configur ation between an mcu and one 33813. data is sent to the 33813 device through th e si input pin. as data is being clocked in to the si pin, other data is being clocke d out of the device by the so outpu t pin. the response data received by the mcu du ring spi communication depends on the previous spi message sent to the device. the spi can be used to read or write data to the configuration and control registers and to rea d or write the data contained in the status registers. the mcu is only allowed to read or clear bits (write zeros) in the status register unless the post enable bit in the control re gister is set. when the post enable bit is set the mcu can read and write zeros or ones to the status register. note that the mcu must clear the post enable bit before operatio n is resumed or the status regi ster will not be updated with fault indications.
analog integrated circuit device data ? freescale semiconductor 35 33813 5.2.1 spi integrity check one spi word is reserved as a spi check message. when bits 12 through 15 are all zero, then the spi will echo the remaining 12-bit spi word sent and will flip bits 12 through 14, bit 15 will remain a 0. this allows the mcu to poll the spi and compare the received message to confirm the integrity of the spi communication channel to the 33813. there is a spi error bit in the spi status register that indicates if an incorrect spi message has been received. the spi error bit in the spi status register is s et whenever any spi message error is detected. important a sclk pulse count strategy has been implemented to ensure integrity of spi communications. only spi messages consisting of 16 sclk pulses will be acknowledged. spi messages consisting of other than 16 sclk pulses will be ignored by the device and reported as a spi error. invalid spi messages, t hat contain invalid commands or addresses will also be flagged as a spi error. figure 16. spi interface with microprocessor two or more 33813 devices may be used in a module system. multiple ics may be spi configured in parallel only. figure 17 demonstrates the configuration. figure 17. spi parallel interface (only) with microprocessor 33813 micro controller receive buffer parallel ports to logic 16-bit shift register shift register mosi si miso so sclk cs parallel ports micro controller 33813 33879a si sclk csb si so sclk csb sclk miso mosi shift register so
analog integrated circuit device data ? freescale semiconductor 36 33813 5.3 functional device operation 5.3.1 power supply the 33813 is designed to operate from vpwr min to vpwr max on the vpwr pin. the vpwr pin supplies power to all internal regulators, and analog and logic circuit blocks. 5.3.1.1 v pp pre-regulator the v pp pre-regulator supplies the input voltage to the v cc and vprot regulators. it uses an external pnp transistor as a pass element. this allows the user to choose the pnp?s size and package considerations to meet the system requirements. the amount of power that the external pnp transistor will have to dissipate depends on the maximum voltage the system can be expected to run at and the maximu m expected current drawn from the v cc and v prot regulators. the vppsens pin is used to feedback the value of the v pp voltage for regulation. since the v pp regulator is not intended to su pply off-the-board loads, there is no short to ground or short to battery pr otection on the output of the external pnp. 5.3.1.2 v cc regulator the v cc regulator output is used for supplying 5.0 volts to the mcu, and for setting communication threshold levels via the internal spi so driver. the v cc regulator contains an internal pass transistor which is protected against over-current. 5.3.1.3 v prot regulator the protected output vprot is a tracking regulator uses the vcc output as a refer ence. since it is expected that the v prot regulator will supply 5.0 volts to external sensors in the vehicle, it is well pr otected against shorts to ba ttery, shorts to ground and over-current. the v prot supply is enabled at power-on but can be disabled via the spi control register. 5.3.2 power on reset (por) applying v pwr and bringing keysw high (vbat) will generate a power on reset (por) and place the device in the normal operating state. the power on reset circui t incorporates a timer to prevent high fr equency transients from causing an erroneous por. upon enabling the device (keysw high), outputs will be activated based on the initial state of t he control register or parallel input. all three supplies, v pp , v cc , and v prot , are enabled when keysw is brought high.
analog integrated circuit device data ? freescale semiconductor 37 33813 figure 18. 33813 functional state diagram 5.3.3 sleep state sleep state is entered when the v bat level signal is removed from the keysw pin and the pwren spi bit is a logic low. in sleep state all outputs and current sources and si nks are off and the device consumes less than i vpwr (ss) a. applying a v bat level to the keysw pin will forc e the device to exit the sl eep state and g enerate a por. table 14. operational states keysw input pwren input batsw output all supplies state l l l off sleep h l h on normal h h h on normal l h l on prepare to shutdown activestates passivestates normal reset* resetb=1 resetb=0 batsw=1 ` sleep start resetb=1 batsw=0 resetb=1 vpwr_uv=1 readyto off shut down resetb=1 batsw=0 pwren=1 spi_reset* resetb=1 uv=undervoltage ov=overvoltage wd=watchdog td=timedelay por=poweronreset &lia *configurationregistersresettodefault,alloutputsoff & = l og i c a nd ^=logicor !=logicnegation
analog integrated circuit device data ? freescale semiconductor 38 33813 5.3.4 normal state the default normal stat e is entered when power is applied to the v pwr and the keysw pins. note that the device is designed to have v pwr present before keysw is brought high. it is acceptable to bring vpwr and keysw high simultaneously, however it is not recommended to bring keysw high while vpwr is low. spi register settings from powe r-on reset (por) are as follows: ? all outputs turned off. ? off state open load detection enabled (lsd) ? default values in the spi configurat ion, control, and status registers. 5.3.5 power on self-test (post) at power on, after a por, it may be desired to go through an init ial power on self-test routine to ensure that the spi is worki ng correctly and the status registers in the 33813 are viable. afte r a por, all the registers in the 33813 contain their ?default? values, as indicated in the spi register tables later in this document. the watchdog is also set to its default timeout value of 10 sec onds, so any post routine must be accomplished within this time fram e or a wd reset may occur. to perform a post routine, the mcu should first send a spi message to set t he post enable bit in the spi control register 1, bit 6. once this bit is set, the status registers are disconnected from the analog and logic portions of the 33813, and are co nnected only to the spi circuitry. the po st can then write various data patterns to the status registers and verify that none of the bits ar e ?stuck? or otherwise unworkin g. note that bits in the status register labelled ?x? are not implemented and when testing these bits may result in erroneous data . after testing all the status registers and co nfirming that they are viable, the status registers can be set back to their defau lt values by clearing the post enable bit back to 0. the post enable bit allows the mcu to write ones (1s) to the status registers. normally, the status register can only be cleared to zeros by the mcu and written ones by the 33813 internal logic. this was designed to prevent the mcu from missing any reported fault bits , and for the 33813, to prevent syst em status errors that could result from the mcu erroneously writing a one (1) to a fault bit. once the post enable bit is set back to a zero (0) by the mcu, the status register returns to the condition where the 33813 can only write ones(1s) to it and the m cu can only write zeros (0s) to it. again, it is important to note that any post routine should be designed to take less than 10 seconds to avoid a watchdog reset from occurring and truncating the post routine because the wd reset will clear the post enable bit as well. the 33813 ic has two modes of opera tion, normal mode, and sleep mode. 5.3.6 watchdog (wd) 5.3.6.1 watchdog normal operation the watchdog is a programmable timer that is used to monito r the operation of the mcu. wh en the mcu is executing code properly, it?s program code should contai n instructions to periodically send a spi message to the watchdog spi control register to refresh the watchdog. the watchdog time r, once refreshed, will reload the time in terval value stored in the spi watchdog configuration register and begin counting time again. under no rmal operating conditions this sequence will continue until the mcu shuts down, typically, when the keysw is turned off. 5.3.6.2 watchdog fault operation in the event that something goes wrong during the mcu program ex ecution, such as an unexpected breakpoint or other program hang-up such as the execution of a halt instruction, the watchdog may not be refreshed. when the wd time interval value programmed in the spi config uration register elapses, the watchdog will issue a resetb pulse . this resetb pulse will cause the mcu to restart it?s program and co rrect operation should be restored. after any resetb (power-on or other), the watchdog spi configurat ion register will contain the default value for the refresh ti me, 10 seconds. the watchdog is also enabled by default. the mcu, in it?s initializatio n (start-up) code, can choose to change this de fault value and/or disable the watchdog by sending a spi command to write new information in the watchdog spi configuration register.
analog integrated circuit device data ? freescale semiconductor 39 33813 5.3.6.3 watchdog spi configuration register there are seven bits in the watc hdog spi configuration register wh ich define the time value that is loaded into the watchdog ti mer. bits 3, 2, 1, 0 are a binary coded decim al (bcd) value from 1 to 10. (11 to 16 are mapped to 10 and 0 is mapped to 1) the remaining three bits, 6, 5, and 4 are the time multiplier values. there are three time multiplier values so only one bit, 6, 5, or 4 may be set at one time. setting more than one bit will re sult in the highest multiplier value getting precedence. bit 7 is the watchdog enable(1) or disable(0) bit. the time multipliers are as follows: bit 6 = x1 seconds (s) bit 5 = x 100 milliseconds (ms) bit 4 = x 10 milliseconds (ms) the register in table 15 shows the watchdog enabled and the time value of 10 seconds. using this technique, time values from 1.0 ms. to 10 seconds can be programmed into the watchdog. 5.3.6.4 watchdog spi control register the watchdog relies on bit 7 of the watchdog spi control register being written as a one (1) to refresh the watchdog timer (i.e . reload the time value from the watchdog spi configuration registe r). the watchdog spi control regi ster can also be loaded with a time value to temporarily set a different value in the watchdog ti mer for the next cycle. when bits 6 thru 0 in the watchdog spi cont rol register are zero, the value stored in the watchdog spi configuration register w ill be loaded into the watchdog timer. if there is a temporary time value written into the watchdog spi control register then that value will be loaded into the watchdog. since the watchdog spi contro l register is automatically cleared to zero when the watchdog timer is loaded, the next watchdog timer load will be from the va lue stored in the watchdog spi configuration register, unless a new temporary time value is again written to the watchdog spi control register. example: to enable and set the watchdog for a timeout value of 200 ms, the mcu will write the followin g byte into the watchdog spi configuration register: in the main loop of the mcu?s program there will be a call to a routine to write the following byte into the watchdog spi contr ol register to refresh the watchdog periodically (must be <200 ms). table 15. watchdog spi configuration register enable/disable x1 sec. x100 ms. x10 ms. 8 4 2 1 1 1 0 0 1 0 1 0 table 16. watchdog spi control register refresh x1 sec. x100 ms. x10 ms. 8 4 2 1 1 0 0 0 0 0 0 0 table 17. watchdog spi configuration register enable/disable x1 sec. x100 ms. x10 ms. 8 4 2 1 1 0 1 0 0 0 1 0 table 18. watchdog spi control register wd refresh x1 sec. x100 ms. x10 ms. 8 4 2 1 1 0 0 0 0 0 0 0
analog integrated circuit device data ? freescale semiconductor 40 33813 5.3.7 low side drivers (lsd) the six open drain low side drivers (lsds) are designed to cont rol various automotive loads such as injectors, fuel pumps, solenoids, lamps, and relays, etc. each driver includes off-st ate open load detection, on-state short to ground detection, shor t- circuit to battery protection, over-current protection, over-tem perature protection, and diagno stic fault reporting via the spi . the lsds are individually controlled through the parallel input pins or/and via the spi. all outputs except rout2 are disabled when the keysw input pin is brought low regardless of the state of the input pins . all outputs, including rout2 are disabled when the resetb pin is low. 5.3.7.1 lsd input logic control the lsds (and the pre-drivers) ar e controlled individually using a combination of the external pin input (if one exists) and/or a spi on/off control bit. the logic can be made to turn the outputs on or off by means of a logica l combination of the external p in ored with the spi control on/off bit or a logical combination of the external pin anded with the spi control on/off bit. a separate or/and select bit is found in the spi conf iguration registers to accomplish this selection. 5.3.7.2 pulse width modulation mode besides just turning the outputs on or off, the outputs can be pulse width modulated (pwm?d) to control the outputs with a variable 0 to 100% duty cycle at a selection of diff erent frequencies. there are two built-in pwm frequencies (100 hz and 1.0 khz) and the external input pin can also be used as either an external pwm frequency input (divided by 100) or a total pwm (frequency and duty cycle) in put. two bits (bits 1, 0) in the spi configuration regist er control which mode of input control is selected. the internal pwm duty cycles (d /c) are controlled by the lower 7 bits in the corresponding spi control register. the duty cycle for the internal pwm is in 1% increments and is specified in t he spi control register as a 7 bit binary word which provides 128 different binary combinations. the binary values of 0000000 to 1100100 represent 0% to 100% and the binary values 1100100 to 1111111 (100 to 127) all map to 100%. the external pwm duty cycles (d/c) are provided by the mc u on the input pin of the corresponding output driver. 5.3.7.3 lsd output protection output protection consists of a dual strat egy which utilizes over-current and/or over-temperature sensing to detect a fault and then automatically control the output to protect the output device from damage. 5.3.7.4 over-current (oc) protection the first protection scheme works by sensing an over-current co ndition by monitoring the voltage on the individual output devic e drain. when the spi configuration retry enable bit is set to a one (1), the default state, during an ov er-current event the device ent ers current limit and will remain in current limit for a fixed time per iod. at the end of this time period the output device will t urn off and wait a delay time roughly 100 times greater than the on time. t he output will try to turn on again after this off time. if the short is still present, the process will start again. this on/off cycling will continue until the output is commanded off or the over-te mperature (ot) on the output device is reached. if the spi configuration register retry enable bit is set to a zero (0), this on/off cycling will not occur and the output will turn off if the over-current threshold is reached. th e output will not turn on again until the output is commanded off and then on again. table 19. external pwm duty cycles bits 1, 0 pwm frequency pwm d/c 00 none or on ext. pin none or on ext. pin 01 100 hz internal 10 1.0 khz internal 11 on ext pin : 100 internal
analog integrated circuit device data ? freescale semiconductor 41 33813 the inrush delay bit, in the spi configuration register for eac h output, when set to a one(1), will prevent the over-current fa ult bit from being set and the over-current protec tion from shutting off the output for t inrush time rather than t sc . 5.3.7.5 temperature limit (ot) protection the second protection scheme works by sensing the local temperat ure of the individual output device. during an over-current event, the device enters current limit and will remain in curre nt limit until the outpu t driver maximum temperature limit is ex ceeded (ot). at this point, the device will shutdow n automatically, regardless of the input st ate. the output will try to turn on agai n only when the junction temperature falls belo w the maximum temperature minus the t lim hysteresis temperatur e value and the input state is commanding the output to be on. the t lim hysteresis value is specified in the static parameter table. the temperature limit (t lim ) protection is independent of the over-current protection and is not controlled by the spi. t lim is always enabled and is always a retry operation. outputs may be used in parallel to drive higher current loads prov ided the turn-off energy of the load does not exceed the ener gy rating of a single output driver. 5.3.7.6 output driver diagnostics over-current (oc), temperature limit (ot) exceeded, short to ground (sg), and open load (ol) conditions are reported through the status register fo r each driver (no sg for the tachometer). only open load and over-current are reported for pre-drivers. t here is also a bit in the spi status register to indicate when any of the lsds or pre-drivers are reporting a fault and when a parti cular output has any of the four possi ble fault conditions present. this makes it easy for the mcu to poll for fault conditions by lo oking for a single bit in one register to detect the presence of any f ault in the circuit. 5.3.7.7 open load pull-down cu rrent enable/disable bit an open load condition is detected by the voltage level on the dr ain of the mosfet in the off state. internal to the device is a pull-down current sink. in the event of an open load the drain voltage is pulled low by the current sink. when the voltage cros ses the open load threshold value, an open load condition is reported . this current sink may be disabled by clearing the appropriat e bit in the in the lsd configuration regist er. when the current sink is disabled, the off-state open load fault status bit will be forced to a logic 0. 5.3.7.8 open load and shor t to battery strategy the injectors, lamps, relays, and tachomet er low side outputs are capabl e of detecting an open load in the off state and short to battery condition in the on state. all f aults are reported through the spi status re gister communication. for open load detecti on, a current source is placed between the mosfet drain pin and gr ound of the ic. an open load fault is reported when the drain voltage is less than the listed threshold. open load fault detect threshold is set internally to the listed threshold and may n ot be programmed. a shorted load fault is report ed when the drain pin voltage is greater than the programmed short threshold voltage when the device is in the on state. the open load and short to battery fault threshold voltage is fixed and cannot be modified via the spi. 5.3.7.9 short to ground strategy the injectors, lamps, and relays (but not the tachometer) low side driver outputs ar e capable of detecting a short to ground when the output is turned on by measuring the current flow in t he output device and comparing it to a known current value. if a short to ground is detected it is annunciated via a bit in the ap propriate spi st atus register. table 20. inrush delay bit inrush delay bit timer value 0 t sc 1 t inrush
analog integrated circuit device data ? freescale semiconductor 42 33813 5.3.8 spi register definitions there are three basic spi register types: configuration registers - used to set the operating mo des and parameters for the 33813 fu nctional blocks. each output can be configured by setting the individual bits in the configuratio n register for that output according to the descriptions in the previous functional descriptions for each particular output. control registers - used to turn outputs on and off and set the pwm duty cycle for outputs that are us ed as pwm outputs. also used to set the temporary operating parameters for the watchdog timer and the vrs circuit. status registers - used to annunciate faults and other values that the mcu may need to act upon. each output and functional block has a status register associated with it and the individual fault bits for each of the faults monitored are contained in these registers. an ?any fault? bit, bit 7, is the or of all the individual fault bits in the register and indicates that one or more of the fault bits is set. there is a system-wide ?any fault? bit in the power supply and any fault status register 13, (bit 7) whose state i s the or of all the other ?any fault? bits in the other status registers. the mcu can monitor this system-wide any fault bit to disco ver if any of the outputs has a fault conditi on present. once the mcu detects the syste m-wide any fault bit =1, then it must interrogate the all the other status registers to determine the actual fault(s) that are present. once a fault bit in any status register is set, by the 33813 circ uit, it can only be cleared by the mcu or by any of the reset actions including a software reset. non-fault bits in the status register can be set and cleared by the 33813 circuit. all existing bits in the status register, bi ts not marked as ?x? can only be cleared by the mcu when the post bit is zero (0). when the post bit is one (1), the mcu can read or write any existing bit in the status re gister. non-existing bits, marked with an ?x ? in the table cannot be changed from the default zero (0) value. 5.3.8.1 existing and non-existi ng bits in the spi registers entries in the following spi registers mark ed with an ?x? are non-existent bits. they are set to zero (0) by default and cannot be changed by reading or writing to them. they shou ld be ignored when testing registers during post. system on/off indicators one of the registers in the stat us register contains the on/off status indicati on of the six lsds and th ree pre-driver outputs (the tachout output is the only output not annunciated in this register). the output is consider to be on (1) whenever all of the following conditions are true: 1. the output is commanded on via the input pin or/and spi bit, subject to the or/and logic condition selected. 2. there are no over-current (oc), short to battery (sb), or over-temperature (ot) faults present. 3. if pwm is enabled, the pwm control is set to a value greater than 0%. 4. there is no reset condition present. (ov, uv, wd, sw) 5. the 33813 is in the normal state. (i.e. keysw =1) note: for rout2, the 33813 can be in either the normal state or the pre-shutdown state if the s hutdown disable (sdd) bit is set and pwren=1. if all of the five conditions above are true, the s ystem on/off bit for that output will be on (1). if any of the five conditions above are false, the s ystem on/off bit for that output will be off (0). 5.3.8.2 model code and revision number one status register is reserved for reporting the model code a nd revision of the 33813 circuits. the model code for the 33813 i s 010. the revision code is the current version number for the circuit. this register is read-only. 5.3.9 spi command summary the spi commands are defined as 16 bits with 4 address control bits and 12 command data bits. there are 7 separate commands that are used to set the operational paramet ers of device. the operational parameters ar e stored internally in 8-bit registers. write commands write the data contained in the present spi word whereas read comma nds have to wait until the next spi command is sent to read the data requested.
analog integrated circuit device data ? freescale semiconductor 43 33813 table 21 defines the commands and default state of the internal registers at por. spi co mmands may be sent to the device at any time while the device is in the normal state. messages sent are acted upon on t he rising edge of the csb input. bit value returned equals bit value sent for this command 5.3.10 spi commands there are seven spi commands that can be issued by the mcu to: ? do a spi check verification ? read the contents of the spi configuration registers ? write the contents of the spi configuration registers ? read the contents of the spi status registers ? write the contents of t he spi status registers ? read the contents of the spi control registers ? write the contents of t he spi control registers 5.3.10.1 spi registers the spi interface consists of a block of four 8-bit read/ write registers. there are three types of spi registers: ? configuration registers - these registers allow the mcu to configure the various parameters and options for the various functional blocks. ? control registers - these registers are used to command the outputs on and off and set the pwm duty cycle values. ? status registers - these registers report back faults and other conditions of the various functional blocks. the following acronyms are use in the spi table: ? oc = over-current, could be short to battery (sb) ? ov = over-voltage ? ot = over-temperature ? ol = open load ? sg = short to ground ? pwm = pulse width modulation table 21. spi command messages command control address bits data bits hex 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spi check 0 0 0 0 0 x* x* x* x* x* x* x* x* x* x* x* x* read configuration register 1 0 0 0 1 <0000> internal register address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 write configuration register 2 0 0 1 0 <0000> internal register address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 read status register 3 0 0 1 1 <0000> internal register address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 write status register 4 0 1 0 0 <0000> internal register address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 read control register 5 0 1 0 1 <0000> internal register address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 write control register 6 0 1 1 0 <0000> internal register address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 spi check response 7 0 1 1 1 x* x* x* x* x* x* x* x* x* x* x* x*
analog integrated circuit device data ? freescale semiconductor 44 33813 ? dc = duty cycle the following conventions are used in the spi register tables: ? all default selections are in bold fonts ? non-default selections are in normal font ? the first selection listed is the default selection ? the binary values shown, (0 or 1) are the default values after a reset has occurred. table 22. spi configuration registers reg # hex 7 6 5 4 3 2 1 0 0 0 injector 1 driver retry enable x x ol current sink enable in- rush delay or/ and pwm freq. 1 pwm freq. 0 ( 0 ) ( 0 ) ( 0 ) ( 1 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 1 1 not used x x x x x x x x ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 2 2 relay 1 driver retry enable x x ol current sink enable in- rush delay or/ and pwm freq. 1 pwm freq. 0 ( 0 ) ( 0 ) ( 0 ) ( 1 ) ( 1 ) ( 0 ) ( 0 ) ( 0 ) 3 3 relay 2 driver retry enable shut down disablesdd x ol current sink enable in- rush delay or/ and pwm freq. 1 pwm freq. 0 ( 0 ) ( 0 ) ( 0 )) ( 1 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 4 4 tachometer driver retry enable vrsout/lsd vrsout/ osc. mode ol current sink enable in- rush delay output freq. 2 output/ pwm freq. 1 output/ pwm freq. 0 ( 0 ) ( 0 ) ( 0 ) ( 0 )?n 16 ( 0 )?n 8 ( 0 )?n 4 ( 0 )?n 2 ( 1 )?n 1 5 5 lamp driver retry enable x x ol current sink enable in- rush delay x pwm freq. 1 pwm freq. 0 ( 0 ) ( 0 ) ( 0 ) ( 1 ) ( 1 ) ( 0 ) ( 0 ) ( 0 ) 6 6 battery switch logic output hsd mode x x x x x pwm freq. 1 pwm freq. 0 ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 7 7 o2 heater pre-driver ign/ gpgd select retry enable x ol current sink x or/ and pwm freq. 1 pwm freq. 0 ( 0 ) ( 0 ) ( 0 ) ( 1 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 8 8 ignition 1 pre-driver ign/ gpgd select retry enable x ol current sink x or/ and pwm freq. 1 pwm freq. 0 ( 1 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 )
analog integrated circuit device data ? freescale semiconductor 45 33813 9 9 not used x x x x x x x x ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 10 a watchdog parameters enable/ disable load time x1 sec load time x100 ms load time x10 ms load time 8 load time 4 load time 2 load time 1 ( 1 ) ( 1 ) ( 0 ) ( 0 ) ( 1 ) ( 0 ) ( 1 ) ( 0 ) 11 b vrs manual parameters threshold 3 threshold 2 threshold 1 threshold 0 filter time 3 filter time 2 filter time 1 filter time 0 ( 0 ) ( 1 ) ( 0 ) ( 1 ) ( 0 ) ( 0 ) ( 1 ) ( 1 ) 12 c vrs automatic parameters mantiss 8 mantiss 4 mantiss 2 mantiss 1 exponent 8 exponent 4 exponent 2 exponent 1 ( 0 ) ( 1 ) ( 1 ) ( 1 ) ( 0 ) ( 0 ) ( 1 ) ( 1 ) 13 d vrs miscellaneous parameters man./ auto disable vrs x high/ low ref de-glitch gnd vrsn inv inputs disable 2.5v cm ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) table 23. spi control registers reg # hex 7 6 5 4 3 2 1 0 0 0 main off/ on control inj1 x rel1 rel2 lamp ign1 x o2h ( 0 /1) ( 0 ) ( 0 /1) ( 0 /1) ( 0 /1) ( 0 /1) ( 0 ) ( 0 /1) 1 1 other off /on control pwren off/ on post enable off/ on x vprot on/ off x batsw off/ on tach off /on reset internal only ( 0 ) ( 0 ) ( 0 ) ( 1 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 2 2 not used x x x x x x x x ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 3 3 relay 1 driver x pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 4 4 relay 2 driver x pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 5 5 tachometer driver x pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 6 6 lamp driver x pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 7 7 batsw x pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 8 8 o2 heater pre-driver x pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 9 a ignition 1 pre-driver x pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) table 22. spi configuration registers reg # hex 7 6 5 4 3 2 1 0
analog integrated circuit device data ? freescale semiconductor 46 33813 10 b not used x x x x x x x x ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 121 c watchdog wdrfsh load time x1 sec load time x100 ms load time x10 ms load time 8 load time 4 load time 2 load time 1 ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 12 d vrs conditioner threshold 3 threshold 2 threshold 1 threshold 0 filter time 3 filter time 2 filter time 1 filter time 0 ( 0 ) ( 0 ) ( 0 ) ( 1 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) table 24. spi status registers reg # hex 7 6 5 4 3 2 1 0 0 0 injector 1 driver faults faults x x x open load ol over - current oc over-temp ot short gnd sg ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 1 1 not used x x x x x x x x ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 2 2 relay 1 driver faults faults x x x open load ol over- current oc over-temp ot short gnd sg ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 3 3 relay 2 driver faults faults x x x open load ol over- current oc over-temp ot short gnd sg ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 4 4 tachometer driver faults faults x x x open load ol over- current oc over-temp ot x ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 5 5 lamp driver faults faults x x x open load ol over- current oc over-temp ot short gnd sg ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 7 7 o2 heater pre-driver faults faults x x x open load ol over- current oc x x ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 8 8 ignition 1 pre-driver faults faults x x x open load ol over- current oc x x ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) table 23. spi control registers reg # hex 7 6 5 4 3 2 1 0
analog integrated circuit device data ? freescale semiconductor 47 33813 9 9 not used x x x x x x x x ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 10 a watchdog state enable/ disable wd timer bit 6 wd timer bit 5 wd timer bit 4 wd timer bit 3 wd timer bit 2 wd timer bit 1 wd timer bit 0 11 b vrs conditioner and iso9141 faults peak 8 peak 4 peak 2 peak 1 x clampacti ve vrsp clampacti ve vrsn iso over- temp ot ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 13 d power supply and any system faults any system faults keysw ( 1/0 ) pwren batsw spi error v prot short to battery v prot over-temp ot v prot short to ground ( 0 ) ( 1 /0) ( 0 /1) ( 0 /1) ( 0 /1) ( 0 /1) ( 0 /1) ( 0 /1) 14 e system on/off indicators inj1 off / on x rel1 off / on rel2 off / on lamp off / on ign1 off / on x o2h off/ on ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) 15 f model code/ revision number* * read only except for post enable model code 2 model code 1 model code 0 rev # rev # rev # rev # rev # ( 0 ) ( 1 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 0 ) ( 1 ) table 24. spi status registers reg # hex 7 6 5 4 3 2 1 0
analog integrated circuit device data ? freescale semiconductor 48 33813 6 typical applications 6.0.1 output off open load fault an output off open load fault is t he detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). the output off open load f ault is detected by comparing t he drain-to-source voltage of th e specific mosfet output to an internally generated reference. each output has one dedicated comparator for this purpose. each output has an internal pull-down current source or re sistor. the pull-down current sources are enabled on power-up and must be enabled for open load detect to function. in cases were the open load detect current is disabled, the status bit will a lways respond with logic 0. the device will only shut down the pull- down current in sleep mode or when disabled via the spi. during output switching, especially with capacitive loads, a false output off open load fault may be triggered. to prevent this false fault from being reported, an internal fault filter of 100 to 450 s is incorporated. the duration for which a false fault may be reported is a function of the load impedance, r ds(on) , c out of the mosfet, as well as the supply voltage, v pwr . the rising edge of csb triggers the built-in fault delay timer. the timer must time out before the fault comparator is enabled to detect a faulted threshold. once the condition ca using the open load fault is removed, the device resumes normal operation. the open load fault, however, will be latched in the outpu t so response register for the mcu to read. 6.0.2 low voltage operation low voltage condition (6.5 v< vpwr <9.0 v) will operate per the command word, however parameter tables may be out of specification and status reported on so pin is not guaranteed. 6.0.3 low side injector driver voltage clamp each injector output of the 33813 incorporates an internal volta ge clamp to provide fast turn-off and transient protection. eac h clamp independently limits the drain-to-source voltage to v cl . the total energy clamped (e j ) can be calculated by multiplying the current area under the current curve (i a ) times the clamp voltage (v cl ) (see figure 19 ). characterization of the output clamps, using a repetitive pulse method at 1.0 a, indicates the maxi mum energy to be 100 mj at 125 ? c junction temperature per output . figure 19. output voltage clamping 6.0.4 reverse battery protection the 33813 device requires external revers e battery protection on the vpwr pin. all outputs consist of a power mosfet wit h an integral substrate diode. during a reverse battery condition, current will flow through the load via the substrat e diode. under this condition load devices will turn on. if load reverse battery protection is desired, a diode must be placed in series with the load. curren t area (i a ) clamp energy (e j = i a x v cl ) drain voltage time dr ai n-to-s ourc e c lamp voltage (v cl = 45 v) dr ain cu rr e nt (i d = 0.3 a) gnd dr ai n-to-s ourc e o n voltage (v ds(o n) ) 50 v) drain-to-source clamp voltage (v cl = 50 v) drain-to-source on voltage (v ds(on) ) drain voltage clamp energy (e j = i a x v cl ) gnd time drain current (i d = 0.3 a)
analog integrated circuit device data ? freescale semiconductor 49 33813 7 packaging 7.1 package mechanical dimensions package dimensions are provided in package drawings. to find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing?s document number. table 25. mechanical dimensions package suffix package outline drawing number 48-pin lqfp-ep ae 98ASA00173D
analog integrated circuit device data ? freescale semiconductor 50 33813 ae suffix 48-pin lqfp-ep 98ASA00173D issue a dimensions shown are provided for reference only (for layout and design, refer to the package outlin e drawing listed in the 98a reference documents table)
analog integrated circuit device data ? freescale semiconductor 51 33813 ae suffix 48-pin lqfp-ep 98ASA00173D issue a
analog integrated circuit device data ? freescale semiconductor 52 33813 ae suffix 48-pin lqfp-ep 98ASA00173D issue a
analog integrated circuit device data ? freescale semiconductor 53 33813 8 revision history revision date description of changes 1.0 8/2012 ? initial release ? removed freescale confidential proprietary on page 1
document number: mc33813 rev. 1.0 8/2012 information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fa bricate any integrat ed circuits on the information in this document. freescale reserves the right to make chang es without further not ice to any products herein. freescale makes no warranty, re presentation, or guarantee regarding the suitability of its products for any particul ar purpose, nor does freescale assume any liability arising out of the application or us e of any product or circ uit, and specifically disclaims any and all liability, including wi thout limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in differ ent applications, and actual performance may vary over time. all operating parameters, in cluding ?typicals,? must be validated for each customer application by customer?s te chnical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net /v2/webservices/freescale/ docs/termsandconditions.htm freescale, the freescale logo, altivec, c-5, codetest, codewarrior, coldfire, c-ware, energy efficient solutions logo, mobilegt, powerquicc, qoriq, qorivva, starcore, and symphony are trademarks of freescale semico nductor, inc., reg. u.s. pat. & tm. off. airfast, beekit, beestack, co ldfire+, corenet, flexis, ma gniv, mxc, platform in a package, processor expert, qoriq qonv erge, quicc engine, ready play, smartmos, turbolink, vybrid, and xtrinsic are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc. how to reach us: home page: freescale.com web support: freescale.com/support

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